To preserve functional characteristics of an integrated circuit, chips are generally packaged into an encapsulating plastic environment, which also provides electrical connections from the chip to a printed wiring board (PWB), onto which the resultant package is to be mounted. An even number of such packaged chips mounted on a PWB typically make up a memory module, for example. The memory module may also comprise a hub distributing signals from a memory controller, via leads, to selected chips.
Particularly in the field of memory module design, there is a strong need to increase memory capacities per PWB, thereby decreasing chip sizes and/or increasing structure densities gained with regard to semiconductor memory design and manufacturing. This is particularly valid in the case of memory modules adapted to server applications, where there are special further requirements with respect to availability and lifetime. It is therefore additionally beneficial to preserve area on a PWB, which has limited dimensions available for positioning chips.
Commonly, an integrated circuit chip package is designed with interconnections to the PWB in the form of TSOP (thin small outline package). Therein, leads contacting electrical pads of the package emerge from peripheral edges of each package in order to contact corresponding pads provided on the PWB. As the rectangular flat body of a package already covers an area on the PWB, the leads and the PWB contacts are positioned beside each package, e.g. along its longitudinal peripheral edges. Such a design disadvantageously consumes valuable space of a PWB.
As a consequence, an alternative package design had been created, which scales the footprint of a package to dimensions of a chip or die encapsulated within the package. According to that design (chip scale packaging, CSP), a set of contacts is provided on a bottom surface of an integrated circuit chip package. These contacts are also known as balls and mainly have a spherical or semispherical form. The contacts are typically arranged as two arrays on the bottom surface, each array having two or three columns and up to, e.g., fifteen lines.
The corresponding pads on the PWB have a similar narrow array design. Advantageously, those pads need no longer be arranged beside the package, rather being located beneath a package according to the CSP design. The PWB area may then be preserved, e.g., for higher density of packages arranged on a circuit board.
Another approach to increase the memory capacity on a board is to stack packaged chips one above the other, or alternatively, to use both sides of a PWB for placing packages, thus employing the third dimension of a board. Stacking is performed by first placing a lowermost package onto a PWB with the set of arrayed contacts being electrically connected to corresponding pads on the board, for example. Then, a further package is placed upon the top surface of the lowermost chip package, the corresponding set of contacts being electrically connected to a so-called flex circuit, which is wrapped around the peripheral edge of the lowermost chip package.
The flex circuit connects both sets of contacts, i.e., the contacts of the lowermost chip package with the respective ones of the further chip package. In the case of two arrays of contacts extending on each side of the package bottom surface, two flex circuits are employed, one for each side. An example for such a module design is provided in U.S. Pat. No. 6,576,992 B1.
However, a problem arises due to signal runtime differences between a connection of the chip of the lowermost package with a controller and a connection of the chip of the further, upper package with that controller. Signal reflections occurring within various contacts along the signal path at different runtimes may considerably deteriorate signal quality.
This feature even worsens, if more than two chips, e.g., four chips or their respective packages, are stacked one above the other as the height of the chip stack considerably increases.